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1 www.semtech.com protection products - railclamp ? ? ? ? ? srv05-4a railclamp ? ? ? ? ? low capacitance tvs diode array description features circuit diagram schematic and pin configuration revision 04/19/2010 railclamp ? low capacitance tvs array is designed to protect high speed data interfaces. this series has been specifically designed to protect sensitive compo- nents which are connected to data and transmission lines from overvoltage caused by electrostatic dis- charge (esd) , electrical fast transients (eft) , and lightning. the unique design incorporates eight surge rated, low capacitance steering diodes and a tvs diode in a single package. during transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. the internal tvs diode prevents over-voltage on the power line, protecting any downstream components. the srv05-4a is in a 6-lead sot-23 package. the leads are finished with lead-free matte tin. each device will protect up to four high-speed lines. they may be used to meet the esd immunity requirements of iec 61000-4-2. the combination of small size, low capacitance, and high surge capability makes them ideal for use in applications such as 10/100 ethernet, usb 2.0, and video interfaces. applications mechanical characteristics ? usb 2.0 power and data line protection ? video graphics cards ? monitors and flat panel displays ? digital visual interface (dvi) ? 10/100 ethernet ? notebook computers ? sim ports ? ieee 1394 firewire ports ? protection for high-speed data lines to iec 61000-4-2 (esd) 15kv (air), 8kv (contact) iec 61000-4-4 (eft) 40a (5/50ns) iec 61000-4-5 (lightning) 12a (8/20 s) ? array of surge rated diodes with internal tvs diode ? small package saves board space ? protects four i/o lines ? low capacitance: 3pf typical ? low clamping voltage ? low operating voltage: 5.0v ? solid-state silicon-avalanche technology ? jedec sot-23 6l package ? pb-free, halogen free, rohs/weee compliant ? molding compound flammability rating: ul 94v-0 ? marking: v05 + date code ? packaging: tape and reel sot-23 6l (top view) 5 13 4 6 2
2 ? 2010 semtech corp. www.semtech.com protection products srv05-4a absolute maximum rating r e t e m a r a pl o b m y ss n o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u e g a t l o v f f o - d n a t s e s r e v e rv m w r 2 o t 5 n i p5v e g a t l o v n w o d k a e r b e s r e v e rv r b i t a m 1 = 2 o t 5 n i p 6v t n e r r u c e g a k a e l e s r e v e ri r v m w r c 5 2 = t , v 5 = 2 o t 5 n i p 5a e g a t l o v d r a w r o fv f i f a m 5 1 =2 . 1v e g a t l o v g n i p m a l cv c i p p s 0 2 / 8 = p t , a 1 = d n u o r g o t n i p o / i y n a 5 . 2 1v e g a t l o v g n i p m a l cv c i p p s 0 2 / 8 = p t , a 5 = d n u o r g o t n i p o / i y n a 5 . 7 1v e c n a t i c a p a c n o i t c n u jc j v r z h m 1 = f , v 0 = d n u o r g o t n i p o / i y n a 35f p v r z h m 1 = f , v 0 = s n i p o / i n e e w t e b 5 . 1f p g n i t a rl o b m y se u l a vs t i n u ) s 0 2 / 8 = p t ( r e w o p e s l u p k a e pp k p 0 0 3s t t a w ) s 0 2 / 8 = p t ( t n e r r u c e s l u p k a e pi p p 2 1a ) r i a ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e ) t c a t n o c ( 2 - 4 - 0 0 0 1 6 c e i r e p d s e v d s e 5 1 8 v k e r u t a r e p m e t g n i r e d l o s d a e lt l ) . c e s 0 1 ( 0 6 2c e r u t a r e p m e t g n i t a r e p ot j 5 2 1 + o t 5 5 -c e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 5 -c electrical characteristics (t=25 o c)
3 ? 2010 semtech corp. www.semtech.com protection products srv05-4a typical characteristics non-repetitive peak pulse power vs. pulse time power derating curve 0 10 20 30 40 50 60 70 80 90 100 110 0 25 50 75 100 125 150 ambient temperature - t a ( o c) % of rated power or i pp clamping voltage vs. peak pulse current pulse waveform forward voltage vs. forward current normalized capacitance vs. reverse voltage 0.00 5.00 10.00 15.00 20.00 25.00 30.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 peak pulse current - i pp (a) clamping voltage -v c (v) waveform parameters: tr = 8s td = 20s 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 forward current - i f (a) forward voltage -v f (v) waveform parameters: tr = 8s td = 20s 0.01 0.1 1 10 0.1 1 10 100 1000 pulse duration - tp (s) peak pulse power - p pk (kw) 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 time (s) percent of i pp e -t td = i pp /2 waveform parameters: tr = 8s td = 20s 0 0.2 0.4 0.6 0.8 1 1.2 1.4 012345 reverse voltage - v r (v) c j (v r ) / c j (v r =0) f = 1 mhz
4 ? 2010 semtech corp. www.semtech.com protection products srv05-4a 3 db/ ch1 s21 log ref 0 db start .030 000 mhz stop 3 000 . 000 000 mhz ch1 s21 log 20 db/ ref 0 db start .030 000 mhz stop 3 000 . 000 000 mhz insertion loss s21 analog cross talk applications information
5 ? 2010 semtech corp. www.semtech.com protection products srv05-4a device connection options for protection of four high-speed data lines the srv05-4a is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. when the voltage on the protected line exceeds the reference voltage (plus diode v f ) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. data lines are connected at pins 1, 3, 4 and 6. the negative reference (ref1) is connected at pin 2. this pin should be connected directly to a ground plane on the board for best results. the path length is kept as short as possible to minimize parasitic inductance. the positive reference (ref2) is connected at pin 5. the options for connecting the positive reference are as follows: 1. to protect data lines and the power line, connect pin 5 directly to the positive supply rail (v cc ). in this configuration the data lines are referenced to the supply voltage. the internal tvs diode prevents over-voltage on the supply rail. 2. the srv05-4a can be isolated from the power supply by adding a series resistor between pin 5 and v cc . a value of 100k is recommended. the internal tvs and steering diodes remain biased, providing the advantage of lower capacitance. 3. in applications where no positive supply reference is available, or complete supply isolation is desired, the internal tvs may be used as the reference. in this case, pin 5 is not connected. the steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the tvs (plus one diode drop). esd protection with railclamps ? ? ? ? ? railclamps are optimized for esd protection using the rail-to-rail topology. along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. consider the situation shown in figure 1 where dis- crete diodes or diode arrays are configured for rail-to- rail protection on a high speed line. during positive duration esd events, the top diode will be forward biased when the voltage on the protected line exceeds data line and power supply protection using vcc as reference data line protection with bias and power supply isolation resistor data line protection using internal tvs diode as reference applications information
6 ? 2010 semtech corp. www.semtech.com protection products srv05-4a pin descriptions the reference voltage plus the v f drop of the diode. for negative events, the bottom diode will be biased when the voltage exceeds the v f of the diode. at first approximation, the clamping voltage due to the charac- teristics of the protection diodes is given by: v c = v cc + v f (for positive duration pulses) v c = -v f (for negative duration pulses) however, for fast rise time transient events, the effects of parasitic inductance must also be consid- ered as shown in figure 2. therefore, the actual clamping voltage seen by the protected circuit will be: v c = v cc + v f + l p di esd /dt (for positive duration pulses) v c = -v f - l g di esd /dt (for negative duration pulses) esd current reaches a peak amplitude of 30a in 1ns for a level 4 esd contact discharge per iec 61000-4-2. therefore, the voltage overshoot due to 1nh of series inductance is: v = l p di esd /dt = 1x10 -9 (30 / 1x10 -9 ) = 30v example: consider a v cc = 5v, a typical v f of 30v (at 30a) for the steering diode and a series trace inductance of 10nh. the clamping voltage seen by the protected ic for a positive 8kv (30a) esd pulse will be: v c = 5v + 30v + (10nh x 30v/nh) = 335v this does not take into account that the esd current is directed into the supply rail, potentially damaging any components that are attached to that rail. also note that it is not uncommon for the v f of discrete diodes to exceed the damage threshold of the protected ic. this is due to the relatively small junction area of typical discrete components. it is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. the railclamp is designed to overcome the inherent disadvantages of using discrete signal diodes for esd suppression. the railclamp?s integrated tvs diode figure 1 - ?rail- figure 1 - ?rail- figure 1 - ?rail- figure 1 - ?rail- figure 1 - ?rail- t t t t t o-rail? pr o-rail? pr o-rail? pr o-rail? pr o-rail? pr o o o o o t t t t t ection t ection t ection t ection t ection t opology opology opology opology opology (first approximation) (first approximation) (first approximation) (first approximation) (first approximation) figure 2 - the effects of parasitic inductance figure 2 - the effects of parasitic inductance figure 2 - the effects of parasitic inductance figure 2 - the effects of parasitic inductance figure 2 - the effects of parasitic inductance when using discrete components to implement when using discrete components to implement when using discrete components to implement when using discrete components to implement when using discrete components to implement rail- rail- rail- rail- rail- t t t t t o-rail pr o-rail pr o-rail pr o-rail pr o-rail pr o o o o o t t t t t ection ection ection ection ection figure 3 - rail- figure 3 - rail- figure 3 - rail- figure 3 - rail- figure 3 - rail- t t t t t o-rail pr o-rail pr o-rail pr o-rail pr o-rail pr o o o o o t t t t t ection using ection using ection using ection using ection using railclam railclam railclam railclam railclam p t p t p t p t p t v v v v v s arra s arra s arra s arra s arra ys ys ys ys ys applications information (continued)
7 ? 2010 semtech corp. www.semtech.com protection products srv05-4a applications information (continued) helps to mitigate the effects of parasitic inductance in the power supply connection. during an esd event, the current will be directed through the integrated tvs diode to ground. the maximum voltage seen by the protected ic due to this path will be the clamping voltage of the device. video interface protection video interfaces are susceptible to transient voltages resulting from electrostatic discharge (esd) and ?hot plugging? cables. if left unprotected, the video interface ic may be damaged or even destroyed. protecting a high-speed video port presents some unique challenges. first, any added protection device must have extremely low capacitance and low leakage current so that the integrity of the video signal is not compromised. second, the protection component must be able to absorb high voltage transients without damage or degradation. as a minimum, the device should be rated to handle esd voltages per iec 61000-4-2, level 4 (15kv air, 8kv contact). the clamping voltage of the device (when conducting high current esd pulses) must be sufficiently low enough to protect the sensitive cmos ic. if the clamping voltage is too high, the ?protected? device may latch-up or be destroyed. finally, the device must take up a relatively small amount of board space, particularly in portable applications such as notebooks and handhelds. the srv05-4a is designed to meet or exceed all of the above criteria. a typical video interface protection circuit is shown in figure 4. all exposed lines are protected including r, g, b, h-sync, v-sync , and the id lines for plug and play monitors. universal serial bus esd protection the srv05-4a may also be used to protect the usb ports on monitors, computers, peripherals or portable systems. each device will protect up to two usb ports (figure 5). when the voltage on the data lines exceed the bus voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. the tvs diode directs the surge to ground. the tvs diode also acts to suppress esd strikes directly on the voltage bus. thus, both power and data pins are protected with a single device. figure 4 - video interface protection figure 5 - dual usb port protection figure 6 - sim port srv05-4a srv05-4a
8 ? 2010 semtech corp. www.semtech.com protection products srv05-4a figure 7 - digital visual interface (dvi) protection dvi protection the small geometry of a typical digital-visual interface (dvi) graphic chip will make it more susceptible to electrostatic discharges (esd) and cable discharge events (cde). transient protection of a dvi port can be challenging. digital-visual interfaces can often transmit and receive at a rate equal to or above 1gbps. the high-speed data transmission requires the protection device to have low capacitance to maintain signal integrity and low clamping voltage to reduce stress on the protected ic. the srv05-4a has a low typical insertion loss of <0.4db at 1ghz (i/o to ground) to ensure signal integrity and can protect the dvi interface to the 8kv contact and 15kv air esd per iec 61000-4-2 and cde. figure 7 shows how to design the srv05-4a into the dvi circuit on a flat panel display and a pc graphic card. the srv05-4a is configured to provide common mode and differential mode protection. the internal tvs of the srv05-4a acts as a 5 volt reference. the power pin of the dvi circuit does not come out through the connector and is not subjected to external esd pulse; therefore, pin 5 should be left unconnected. connecting pin 5 to vcc of the dvi circuit may result in damage to the chip from esd current. 10/100 ethernet protection ethernet ics are vulnerable to damage from electro- static discharge (esd). the internal protection in the phy chip, if any, often is not enough due to the high energy of the discharges specified by iec 61000-4-2. if the discharge is catastrophic, it will destroy the protected ic. if it is less severe, it will cause latent failures that are very difficult to find. in a typical 10/100 system, the twisted-pair interface for each port consists of two differential signal pairs: one for the transmitter and one for the receiver, with the transmitter input being the most sensitive to damage. the fatal discharge occurs differentially across the transmit or receive line pair and is capaci- tively coupled through the transformer to the ethernet chip. figure 8 shows how to design the srv05-4a on the line side of a 10/100 ethernet port to provide differential mode protection. the common mode isolation of the transformer will provide common mode protection to the rating of the transformer isolation which is usually >1.5kv. figure 9 shows how to implement the srv05-4a on the ic side of the 10/ 100 ethernet circuit.
9 ? 2010 semtech corp. www.semtech.com protection products srv05-4a figure 8 - 10/100 ethernet differential protection figure 9 - 10/100 ethernet differential and common mode protection srv05-4a srv05-4a
10 ? 2010 semtech corp. www.semtech.com protection products srv05-4a outline drawing - so-8 land pattern -sot23 6l outline drawing -sot23 6l .110 bsc .037 bsc detail aaa c seating ccc c 2x n/2 tips 2x e/2 6 see detail a1 a a2 bxn a .008 12 n e .060 .114 .063 .122 .010 - 6 a 0.20 1.60 3.10 2.80 bsc 0.95 bsc .069 1.50 2.90 .020 0.25 1.75 0.50 - ei l (l1) c 01 0.25 plane gage h 2.80 .110 bbb c a-b d 0 .008 - .004 .012 .003 (.024) .018 - .035 .000 .035 - - .045 0.10 0.20 10 0 - 10 1.15 (0.60) 0.45 .024 .009 0.30 0.08 .057 .051 .006 0.00 .90 0.90 0.22 0.60 - 0.15 1.45 1.30 - - 1.90 bsc .075 bsc a e1 d e b c plane d datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. notes: 1. 2. -a- -b- -h- side view nom inches dimensions l1 aaa bbb ccc 01 n dim c e e1 l e1 e d a1 a2 b a min millimeters max min nom max dimensions inches y z dim g p x c millimeters p (c) z y g .043 .141 .055 (.098) .037 .024 1.40 (2.50) 0.95 0.60 1.10 3.60 x dimensions inches y z dim g p x c millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1.
11 ? 2010 semtech corp. www.semtech.com protection products srv05-4a contact information semtech corporation protection products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 r e b m u n t r a ph s i n i f d a e l r e p y t q l e e r e z i s l e e r t c t a 4 - 5 0 v r sn i t e t t a m0 0 0 , 3h c n i 7 marking codes ordering information tape and reel specification e p a t h t d i w ) x a m ( , bd1 de f k ) x a m ( p0 p2 p) x a m ( tw m m 8 m m 2 . 4 ) 5 6 1 . ( m m 1 . 0 + 5 . 1 m m 0 . 0 - m m 0 . 1 5 0 . 0 0 1 . 0 5 7 . 1 m m 5 0 . 0 5 . 3 m m m m 4 . 2 1 . 0 0 . 4 m m 1 . 0 0 . 4 m m 5 0 . 0 0 . 2 m m m m 4 . 0 m m 0 . 8 m m 3 . 0 + m m 1 . 0 - 0 a0 b0 k m m 5 0 . 0 - / + 3 2 . 3m m 5 0 . 0 - / + 7 1 . 3m m 5 0 . 0 - / + 7 3 . 1 yw = 2 - alphanumeric characters for date code v05 yw user direction of feed pin 1 location

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